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 THC63LVDF84B/THC63LVDF64B_Rev2.0
THC63LVDF84B/THC63LVDF64B
LVDS 24Bit/18Bit COLOR HOST-LCD PANEL INTERFACE RECEIVER
General Description
The THC63LVDF84B/THC63LVDF64B receiver supports wide VCC range(2.5~3.6V). At single 2.5V supply, the THC63LVDF84B/THC63LVDF64B reduces EMI and power consumption. The THC63LVDF84B receiver convert the four LVDS(Low Voltage Differential Signaling) data streams back into 28bits of CMOS/TTL data with falling edge clock. At a transmit clock frequency of 85MHz, 28bits of RGB data and 4bits of LCD timing and control data (HSYNC, VSYNC, CNTL1, CNTL2) are transmitted at a rate of 2.3Gbps. Also the THC63LVDF64B receiver convert the three LVDS data streams back into 21bits of CMOS/TTL data with falling edge clock. At a transmit clock frequency of 85MHz, 21bits of RGB data and 4bits of LCD timing and control data (HSYNC, VSYNC, CNTL1, CNTL2) are transmitted at a rate of 1.78Gbps.
Features
* Wide VCC range: 2.5~3.6V * Wide dot clock range: 20-85MHz suited for VGA, *
SVGA, XGA and SXGA (VCC=3.0~3.6V) Wide dot clock range: 20-70MHz suited for VGA, SVGA, XGA and SXGA (VCC=2.5V~3.6V)
* PLL requires No external components * Rx power consumption < 80mW @VCC 2.5V,
65MHz Grayscale
* Power-Down Mode * Low profile 56 Lead or 48 Lead TSSOP Package * Pin compatible with THC63LVDF84A/F64A
Block Diagram
THC63LVDF84B CMOS/TTL OUTPUT LVDS TO TTL PARALLEL RA0-6 RA +/RB0-6 RC0-6 RD0-6 DATA (LVDS) RB +/RC +/-
THC63LVDF64B CMOS/TTL OUTPUT LVDS TO TTL PARALLEL
RA +/RB +/RC +/RD +/-
7 7 7 7
7 7 7
RA0-6 RB0-6 RC0-6
DATA (LVDS)
CLOCK (LVDS) RCLK +/20 to 85MHz
PLL
RECEIVER CLOCK OUT (20 to 85MHz) /PDWN
CLOCK (LVDS) RCLK +/20 to 85MHz
PLL
RECEIVER CLOCK OUT (20 to 85MHz) /PDWN
(140-595Mbit/On Each LVDS Channel)
Copyright 2001-2003 THine Electronics, Inc. All rights reserved
1
THine Electronics, Inc.
THC63LVDF84B/THC63LVDF64B _Rev2.0
Pin Out
THC63LVDF84B
RC3 RD6 RC4 GND RC5 RC6 RD0 LVDSGND RARA+ RBRB+ LVDSVCC LVDSGND RCRC+ RCLKRCLK+ RDRD+ LVDSGND PLLGND PLLVCC PLLGND /PDWN CLKOUT RA0 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 VCC RC2 RC1 RC0 GND RB6 RD5 RD4 VCC RB5 RB4 RB3 GND RB2 RD3 RD2 VCC RB1 RB0 RA6 GND RA5 RD1 RA4 RA3 VCC RA2 RA1 RC3 RC4 GND RC5 RC6 N/C LVDSGND RARA+ RBRB+ LVDSVCC LVDSGND RCRC+ RCLKRCLK+ LVDSGND PLLGND PLLVCC PLLGND /PDWN CLKOUT RA0
THC63LVDF64B
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 VCC RC2 RC1 RC0 GND RB6 VCC RB5 RB4 RB3 GND RB2 VCC RB1 RB0 RA6 GND RA5 RA4 RA3 VCC RA2 RA1 GND
Copyright 2001-2003 THine Electronics, Inc. All rights reserved
2
THine Electronics, Inc.
THC63LVDF84B/THC63LVDF64B _Rev2.0
THC63LVDF84B Pin Description
Pin Name RA+, RARB+, RBRC+, RCRD+, RDRCLK+, RCLKRA0~RA6 RB0~RB6 RC0~RC6 RD0~RD6 CLKOUT /PDWN VCC GND LVDSVCC LVDSGND PLLVCC PLLGND Pin # 9, 10 11, 12 15, 16 19, 20 17, 18 27,29,30,32,33,35,37 38,39,43,45,46,47,51 53,54,55,1,3,5,6 7,34,41,42,49,50,2 26 25 31,40,48,56 4,28,36,44,52 13 8,14,21 23 22,24 Type LVDS IN LVDS IN LVDS IN LVDS IN LVDS IN OUT OUT OUT OUT OUT IN Power Ground Power Ground Power Ground Pixel Clock Output H: Normal operation L: Power down (all outputs are pulled to ground ) Power Supply Pins for TTL outputs and digital circuitry Ground Pins for TTL outputs and digital circuitry Power Supply Pin for LVDS inputs Ground Pins for LVDS inputs Power Supply Pin for PLL circuitry Ground Pins for PLL circuitry Pixel Data Outputs LVDS Clock Inputs LVDS Data Inputs Description
THC63LVDF64B Pin Description
Pin name RA+, RARB+, RBRC+, RCRCLK+, RCLKRA0~RA6 RB0~RB6 RC0~RC6 CLKOUT /PDWN VCC GND LVDSVCC LVDSGND PLLVCC PLLGND Pin # 8,9 10,11 14,15 16,17 24,26,27,29,30,31,33 34,35,37,39,40,41,43 45,46,47,1,2,4,5 23 22 28,36,42,48 3,25,32,38,44 12 7,13,18 20 19,21 Type LVDS IN LVDS IN LVDS IN LVDS IN OUT OUT OUT OUT IN Power Ground Power Ground Power Ground Pixel Clock Output H: Normal operation L: Power down ( all outputs are pulled to ground) Power Supply Pins for TTL outputs and digital circuitry Ground Pins for TTL outputs and digital circuitry Power Supply Pin for LVDS inputs Ground Pins for LVDS inputs Power Supply Pin for PLL circuitry Ground Pins for PLL circuitry Pixel Data Outputs LVDS Clock Inputs LVDS Data Inputs Description
Copyright 2001-2003 THine Electronics, Inc. All rights reserved
3
THine Electronics, Inc.
THC63LVDF84B/THC63LVDF64B _Rev2.0
Electrical Characteristics CMOS/TTL DC SPECIFICATIONS
VCC = 2.5V ~ 3.6V, Ta = -10 C ~ +70 C Symbol VIH VIL VOH1 VOL1 VOH2 VOL2 IIN Parameter High Level Input Voltage Low Level Input Voltage High Level Output Voltage Low Level Output Voltage High Level Output Voltage Low Level Output Voltage Input Current VCC= 3.0V ~ 3.6V IOH = -4mA VCC = 3.0V ~ 3.6V IOL = 4mA VCC= 2.5V ~ 3.0V IOH = -2mA VCC = 2.5V ~ 3.0V IOL = 2mA
0V VIN VCC
Conditions
Min. 2.0 GND 2.4
Typ.
Max. VCC 0.8
Units V V V
0.4 2.1 0.4
10
V V V uA
LVDS RECEIVER DC SPECIFICATIONS
VCC = 2.5V ~ 3.6V, Ta = -10 C ~ +70 C Symbol VTH VTL IIN Parameter Differential Input High Threshold Differential Input Low Threshold Input Current Conditions VOC = +1.2V VIN = +2.4V/0V VCC = 3.6V Min. -100
10
Typ.
Max. 100
Units mV mV uA
Absolute Maximum Ratings1
Supply Voltage (Vcc) CMOS/TTL Input Voltage CMOS/TTL Output Voltage LVDS Receiver Input Voltage Junction Temperature Storage Temperature Range Resistance to soldering heat Maximum Power Dissipation@25 C -0.3 to +4V -0.3 to (Vcc + 0.3V) -0.3V to (Vcc + 0.3V) -0.3V to (Vcc + 0.3V) +125 C -55 C to +150 C +260 C /10sec 0.5W
1. "Absolute Maximum Ratings" are those valued beyond which the safety of the device can not be guaranteed. They are not meant to imply that the device should be operated at these limits. The tables of "Electrical Characteristics" specify conditions for device operation.
Copyright 2001-2003 THine Electronics, Inc. All rights reserved
4
THine Electronics, Inc.
THC63LVDF84B/THC63LVDF64B _Rev2.0
Supply Current
VCC = 2.5V ~ 3.6V, Ta = -10 C ~ +70 C Symbol IRCCG Parameter Receiver Supply Current 16Grayscale Pattern Receiver Supply Current Worst Case Pattern Receiver Power Down Supply Current Condition(*) CL=8pF, VCC=3.3V CL=8pF, VCC=2.5V CL=8pF, VCC=3.3V CL=8pF, VCC=2.5V /PDWN = L f = 65MHz f = 85MHz f = 65MHz f = 65MHz f = 85MHz f = 65MHz Typ. 41 52 30 72 84 42 Max. 53 64 42 94 96 64 10 Units mA mA mA mA mA mA A
IRCCW IRCCS
16 Gray Scale Pattern CLKIN Rx0 Rx1 Rx2 Rx3 Rx4 Rx5 Rx6
Worst Case Pattern CLKIN EVEN RxIN ODD RxIN
Copyright 2001-2003 THine Electronics, Inc. All rights reserved
5
THine Electronics, Inc.
THC63LVDF84B/THC63LVDF64B _Rev2.0
Switching Characteristics
VCC= 2.5V ~ 3.6V, Ta = -10 C ~ +70 C Symbo l tRCP tRCH tRCL tRCD tRS tRH tTLH tTHL tRIP1 tRIP0 tRIP6 tRIP5 tRIP4 tRIP3 tRIP2 tRPLL Parameter CLK OUT Period CLK OUT High Time CLK OUT Low Time RCLK +/- to CLK OUT Delay TTL Data Setup to CLK OUT TTL Data Hold from CKL OUT TTL Low to High Transition Time TTL High to Low Transition Time Input Data Position0 (T = 11.76ns) Input Data Position1 (T = 11.76ns) Input Data Position2 (T = 11.76ns) Input Data Position3 (T = 11.76ns) Input Data Position4 (T = 11.76ns) Input Data Position5 (T = 11.76ns) Input Data Position6 (T = 11.76ns) Phase Lock Loop Set -0.4 T/7-0.4 2T/7-0.4 3T/7-0.4 4T/7-0.4 5T/7-0.4 6T/7-0.4 0.35T-0.3 0.45T-1.6 2.0 1.8 0.0 T/7 2T/7 3T/7 4T/7 5T/7 6T/7 3.0 3.0 0.4 T/7+0.4 2T/7+0.4 3T/7+0.4 4T/7+0.4 5T/7+0.4 6T/7+0.4 10.0 VCC = 3.0 - 3.6V VCC = 2.5 - 3.6V Min. 11.76 14.28 Typ. T T 4T/7 3T/7 5T/7 Max. 50.0 50.0 Unit s ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms
AC Timing Diagrams TTL Output
80% 20%
80% 8pF
TTL Output
20%
TTL Output Load tTLH tTHL
Copyright 2001-2003 THine Electronics, Inc. All rights reserved
6
THine Electronics, Inc.
THC63LVDF84B/THC63LVDF64B _Rev2.0
AC Timing Diagrams
tRIP2 tRIP3 tRIP4 tRIP5 tRIP6 tRIP0 tRIP1
Rx+/-
Rx6
Rx5
Rx4
Rx3
Rx2
Rx1
Rx0
RCLK+
Vdiff = 0V tRCD tRCP tRCH VCC/2 VCC/2 tRS tRH DATA VALID tRCL
Vdiff = 0V
CLKOUT
VCC/2
VCC/2
Rx0 - Rx6
DATA VALID
VCC/2
VCC/2
Note: 1) Vdiff = (RA+) - (RA-), ...... (RCLK+) - (RCLK-)
Copyright 2001-2003 THine Electronics, Inc. All rights reserved
7
THine Electronics, Inc.
THC63LVDF84B/THC63LVDF64B _Rev2.0
AC Timing Diagrams
Phase Lock Loop Set Time
/PDWN
VCC/2
3.6V
VCC
VCC/2
tRPLL
RCLK+/-
CLKOUT
VCC/2
Copyright 2001-2003 THine Electronics, Inc. All rights reserved
8
THine Electronics, Inc.
THC63LVDF84B/THC63LVDF64B _Rev2.0
Package
56 Lead Molded Thin Shrink Small Outline Package, JEDEC
14.0 0.1 56 29
Unit : millimeters
8.1 0.1 4.05
6.1 0.1
1
28 (1.0) 1.2 MAX 0.10 0.05
0.50 TYP
0.20 TYP
48 Lead Molded Thin Shrink Small Outline Package, JEDEC
Unit : millimeters 25
12.5 0.1 48
8.1 0.1 4.05
6.1 0.1
1
24 (1.0) 1.2 MAX 0.10 0.05
0.50 TYP
0.20 TYP
Copyright 2001-2003 THine Electronics, Inc. All rights reserved
9
THine Electronics, Inc.
THC63LVDF84B/THC63LVDF64B _Rev2.0
Notes to Users:
1. The contents of this data sheet are subject to change without prior notice. 2. Circuit diagrams shown in this data sheet are examples of application. Therefore, please pay sufficient attention when designing circuits. Even if there are incorrect descriptions, we are not responsible for any problem due to them. Please note that incorrect descriptions sometimes cannot be corrected immediately if found. 3. Our copyright and know-how are included in this data sheet. Duplication of the data sheet and disclosure to other persons are strictly prohibited without our permission. 4. We are not responsible for any problems of industrial proprietorship occurring during THC63LVDF84B/ THC63LVDF64B use, except for those directly related to THC63LVDF84B/THC63LVDF64B's structure, manufacture or functions. THC63LVDF84B/THC63LVDF64B is designed on the premise that it should be used for ordinary electronic devices. Therefore, it shall not be used for applications that require extremely high-reliability (space equipment, nuclear control equipment, medical equipment that affects people's lives, etc.). In addition, when using THC63LVDF84B/THC63LVDF64B for traffic signals, safety devices and control/safety units in transportation equipment, etc., appropriate measures should be taken. 5. We are making the utmost effort to improve the quality and reliability of our products. However, there is a very slight possibility of failure in semiconductor devices. To avoid damage to social or official organizations, much care should be taken to provide sufficient redundancy and fail-safe design. 6. No radiation-hardened design is incorporated in THC63LVDF84B/THC63LVDF64B. 7. Judgment on whether THC63LVDF84B/THC63LVDF64B comes under strategic products prescribed by the Foreign Exchange and Foreign Trade Control Law is the user's responsibility. 8. This technical document was provisionally created during development of THC63LVDF84B/THC63LVDF64B, so there is a possibility of differences between it and the product's final specifications. When designing circuits using THC63LVDF84B/THC63LVDF64B, be sure to refer to the final technical documents.
THine Electronics, Inc. Wakamatsu Bldg, 6F 3-3-6, Nihombashi-Honcho, Chuo-ku, Tokyo, 103-0023 Japan Tel: 81-3-3270-0666 Fax: 81-3-3270-0688
Copyright 2001-2003 THine Electronics, Inc. All rights reserved 10 THine Electronics, Inc.


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